As for an STL receiving apparatus for receiving digital broadcasting signals transmitted from a broadcasting station or studio to a transmitting station, there is known a digital data receiving apparatus for receiving plural redundant broadcasting signals through plural receivers which includes a switching unit for selecting one of the plural digital broadcasting signals.
FIG. 4 shows a block diagram illustrating an apparatus for receiving digital data disclosed in the patent application filed by the inventors prior to this patent application. Referring to FIG. 4, an STL receiving apparatus 100 selects TS (transport stream) data and a TS clock based on digital broadcasting signals received through an antenna 10 to send the selected TS data and TS clock to a first and a second broadcaster 50A and 50B. Further, the STL receiving apparatus 100 includes a first receiver 20A and a second receiver 20B, a switching control device 40 and a switching unit 300.
In the STL receiving apparatus 100, the digital broadcasting signals received through the antenna 10 are inputted to the first receiver 20A and the second receiver 20B. The inputted digital broadcasting signals are transformed into IF (intermediate frequency) signals by down converters 21A and 21B and then demodulated by demodulators 22A and 22B, which are installed in the receivers 20A and 20B, respectively. Dividers 23A and 23B divide the demodulated digital data obtained by the demodulators 22A and 22B into TS (transport stream) data and TS clocks.
A first TS clock 30-1 and a first TS data 30-2 outputted from the first receiver 20A are inputted to a first synchronizing controller 33A, which detects a synchronous code included in the first TS data 30-2. A first write reset signal CTL for a first memory 34A is generated based on the synchronous code. The first TS data 30-2 is written into the first memory 34A in response to the first TS clock 30-1 and the first write reset signal CTL generated by the first synchronizing controller 33A.
Likewise, a second TS data 30-4 is written into a second memory 34B in response to a second TS clock 30-3 and a second write reset signal CTL generated by the second synchronizing controller 33B based on the second TS data 30-4.
A clock control device 35 receives the first and the second TS clock 30-1 and 30-3 and outputs a post-switching clock 30-5 pursuant to a switching control signal 30-7 outputted by a switching control device 40. A data control device 37 receives the post-switching clock 30-5 from the clock control device 35 as well as, for example, the first TS data 30-2 from the first synchronizing controller 33A and the second TS data 30-4 from the second synchronizing controller 33B to output a read reset signal 30-19 to the memories 34A and 34B. The read reset signal 30-19 is outputted from the data control device 37, for example, after a time period MAXW from a rising edge of the first write reset signal CTL and a time period MINX from a rising edge of the second write reset signal CTL, as shown in FIG. 5. The data control device 37 also outputs a selection signal to a selector 31. The selector 31 selects one of the two TS read datas (TS read data 30-17 and TS read data 30-18) in response to the selection signal outputted from the data control device 37 and outputs a post-switching data 30-6. If, for example, the first TS read data 30-17 is corrupted but the second TS read data 30-18 is not, the second TS read data is selected and outputted as the post-switching data 30-6.
The post-switching clock 30-5 is inputted to the first and the second memory 34A and 34B and used for reading data from the memories. The post-switching clock 30-5 is also inputted to the data control device 37 for generating the read reset signal 30-19 to the first memory 34A and the second memory 34B.
As a result, the first memory 34A and the second memory 34B are controlled by the same clock, i.e., the post-switching clock 30-5, and the same control signal, i.e., the read reset signal 30-19, when reading the memories 34A and 34B. Therefore, the first TS read data 30-17 outputted from the memory 34A and the second TS read data 30-18 outputted from the memory 34B are synchronous.
Hereinafter, waveforms of the signals generated in the apparatus 100 will be described with reference to FIG. 5. As shown in FIG. 5, the first TS read data 30-17 and the second TS read data 30-18 are read out at the same time because the memories 34A and 34B are read in response to the same read reset signal. Therefore, the first and the second data can be seamlessly switched into the post-switching data 30-6 by the selector 31, as illustrated in FIG. 5. In the case shown in FIG. 5, for example, signals 1-(0), 1-(1), 2-(2), 2-(3) and 1-(4) are outputted sequentially.
As described above, by using the apparatus for receiving digital data shown in FIG. 4, a plurality of data streams (data, clocks) obtained by demodulating plural redundant signals received in plural receivers can be switched so that a certain data stream can be switched into another data stream without causing an interruption of clocks or data.
However, the apparatus of FIG. 4 has such a drawback as explained hereinafter. Referring to FIG. 4, the first TS clock 30-1 and the first TS data 30-2 outputted from the first receiver 20A are inputted to the first synchronizing controller 33A. The synchronizing controller 33A detects a synchronization byte (47h) included in the first TS data 30-2 to generate the first write reset signal CTL for the first memory 34A. Using a synchronization byte (47h) in each TS data packet, a time delay between the first and the second data should not be greater than 1 TS (204 W) in order to properly handle the time delay, wherein 1 TS is 50 μs at a bit rate of 32.508 Mbps.
FIG. 4 illustrates a case where the signals received by the antenna 10 are distributed through plural paths, a plurality of data streams are obtained by demodulating the received signals and a data stream selected from the plurality of data streams is outputted. In this case, a time delay between the receivers 20A and 20B is so small (1 to 10 μs) that it is possible to avoid problems due to the time delay.
However, e.g., in case where the receiver 20A serves as a microwave transmission path and the receiver 20B serves as an optical transmission path, a time delay greater than 1 TS may occur since each signal is received through a different path.
In other words, when transmitting signals from a broadcasting studio or station to a repeater station, i.e., an STL receiving apparatus, signals sent through the microwave transmission path are transmitted directly to the receiver 20A whereas signals sent through the optical transmission path goes through a longer path because an optical fiber constituting the optical transmission path is installed underground. As a result, a time delay between the corresponding transmission paths becomes greater than 1 TS, making it difficult to perform a seamless data switching.